000			01763nam a2200229 a 4500
001			ASIN1402074018
003			OSt
005			20200227135003.0
008			150306s2003 xxu eng d
020			_a1402074018 (hardcover)
020			_a9780156029698 (hardcover)
037			_bPak Book _cPKR 1970.10
040			_cAUMC
082			_a621.392
100	1		_aBergeron, Janick.
245	1	0	_aWriting testbenches : _cJanick Bergeron.
260			_aNew Delhi: _bSpringer, _c2006.
300			_axxvi,412 p. ; _c( R 10, Sh 03)
520			_amental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches� all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test� benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification.
856	4	0	_3Amazon.com _uhttp://www.amazon.com/exec/obidos/ASIN/1402074018/chopaconline-20
942			_2ddc _cBK
999			_c19352 _d19352