| 000 | 01440nam a2200265 a 4500 | ||
|---|---|---|---|
| 001 | ASIN0387333991 | ||
| 003 | OSt | ||
| 005 | 20200227134852.0 | ||
| 008 | 150227s2006 xxu eng d | ||
| 020 | _a0387333991 (hardcover) | ||
| 020 | _a9781852332631 (hardcover) | ||
| 037 |
_bPak Book _cPKR 980.10 |
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| 040 | _cAUMC | ||
| 082 | _a621.392 | ||
| 100 | 1 | _aSutherland, Stuart. | |
| 245 | 1 | 0 |
_a Verilog and System........... _b / _cStuart Sutherland, Simon Davidmann, Peter Flake, P. Moorby. |
| 260 |
_aNew Delhi : _bSpringer, _c2007. |
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| 300 |
_axxii,214 p. ; _c( R 10, Sh 03) |
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| 520 | _aIn its updated second edition, this book has been extensively revised on a chapter by chapter basis. The book accurately reflects the syntax and semantic changes to the SystemVerilog language standard, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter explaining the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools. | ||
| 700 | 1 | _aDavidmann, Simon. | |
| 700 | 1 | _aFlake, Peter. | |
| 700 | 1 | _aMoorby, P. | |
| 856 | 4 | 0 |
_3Amazon.com _uhttp://www.amazon.com/exec/obidos/ASIN/0387333991/chopaconline-20 |
| 942 |
_2ddc _cBK |
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| 999 |
_c19277 _d19277 |
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