000			01964nam a2200241 a 4500
001			ASIN0387260498
003			OSt
005			20200227134850.0
008			150227s2005 xxu eng d
020			_a0387260498 (hardcover)
020			_a9780387260495 (hardcover)
037			_bPak Book _cPKR 1772.10
040			_cAUMC
082			_a621.392
100	1		_aVijayaraghavan, Srikanth.
245	1	2	_aA practical guide for systemverilog assertions / _cSrikanth Vijayaraghavan, Meyyappan Ramanathan.
260			_aNew Delhi : _bSpringer, _c2005.
300			_axxii,334 p. ; _c( R 10, Sh 03)
520			_aSystemVerilog language consists of three�categories of features�-- Design, Assertions and Testbench.� Assertions add a whole new dimension to the ASIC verification process.���Engineers are used to writing testbenches in verilog that help�verify their design.� Verilog is a procedural language and is very limited in capabilities to handle the complex ASICs built today.� SystemVerilog assertions (SVA) is a declarative language.� The temporal nature of the language provides excellent control over time and allows mulitple processes to execute simultaneously.� This provides the�engineers a very strong tool to solve their verification problems.� The language is still new and the thinking is very different from the�user's perspective when compared to standard verilog language.� There is not enough expertise or intellectual property available as of today in the field.� While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems.� This book is a practical guide that will help people to understand this new language and adopt assertion based verification methodology quickly.
700	1		_aRamanathan, Meyyappan.
856	4	0	_3Amazon.com _uhttp://www.amazon.com/exec/obidos/ASIN/0387260498/chopaconline-20
942			_2ddc _cBK
999			_c19275 _d19275